Importance

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Abstract

A plurality of tristate circuits (TSG1, TSG2, TSG3) each include an input circuit (NAND1, NOR1; NAND2, NOR2; NAN3, NOR3) for receiving first and second control signals (.phi.goe1*, in1; .phi.goe2*, in2; .phi.goe3*, in3) and a tristate output circuit (Q1p, Q1n; Q2p, Q2n; Q3n). The input circuits further receiving a test signal (TEST*). The tristate circuits each include a tristate output (OT1; OT2; OT3) which connects the output circuit to a signal line (SL). The signal line is connected with a test output circuit (Ru, Q4p, Q4n, Rd). The tristate output circuits each include a MOSFET (Q1p; Q2p; Q3p) for selectively connecting the tristate output (OT1; OT2; OT3) with a power supply terminal (Vdd) and a MOSFET (Q1n; Q2n; Q3N) for connecting the tristate output with a ground voltage level (Vss). In one test mode, a test signal is applied (i) which causes the MOSFETs (Q1p; Q2p; Q3p) to cut off forcibly cutting the current path between the power supply terminal (Vdd) and the signal line (SL) and (ii) causes the test output circuit pull-up transistor (Q4p) to close connecting a pull up resistance (Ru) between the power supply voltage level (Vdd) and the signal line (SL). In this mode, the voltage level of the signal line is set to a logic 1 or a logic 0. In this manner, the operation is equivalent to a selector for forcing the signal line to the voltage level of a logic 1 or a logic 0.

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First Claim