Errorless line protection switching in asynchronous transer mode (ATM) communications systems
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United States of America Patent
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Feb 8, 1994
Grant Date -
N/A
app pub date -
Mar 17, 1992
filing date -
Mar 17, 1992
priority date (Note) -
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status (Latency Note)
Importance
Abstract
An errorless line protection apparatus involves receipt of data from an active line and a standby line. A determination is made as to whether the data from the active line leads or lags the data on the standby line. A switching system directs the leading data to a lead channel containing a controllable amount of time delay up to the maximum amount that the leading data is expected to led the lagging data. Lagging data is directed to a lag channel. A selected one of the data from the lead channel or the lag channel is delivered to an output line.
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