Process of fabricating a high capacitance storage node
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United States of America Patent
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Feb 15, 1994
Grant Date -
N/A
app pub date -
Feb 3, 1993
filing date -
Feb 3, 1993
priority date (Note) -
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Abstract
A method for the fabrication of high density dynamic random access memory (DRAM) devices with particular emphasis on the capacitor formation. The capacitor is formed using layers of doped and undoped polysilicon. The layers are patterned anisotropically so as to have their remaining portions over the planned capacitor areas, wherein a portion of the layers remains over both the gate structure and the field oxide areas. Then selective etching of the portion of doped polysilicon layer is accomplished using phosphoric acid at a temperature of more than abut 140.degree. C. to create an undercut of the undoped polysilicon layer. The capacitor is completed using a dielectric layer and a top electrode layer.
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