Importance

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Abstract

Complications of timing recovery in an ATM receiver are overcome by employing a first phase lock loop including a phase comparator, filter, voltage controlled oscillator (VCO) and output counter to lock to systems clock reference (SCR) values which are asynchronously received from a remote ATM transmitter. The SCR values represent the instantaneous values of a system timing clock (STC) at the instant of transmission of the asynchronous SCR values. In the receiver, the output counter is first set to the value of the initial received SCR value so that the derived STC is available for decoding data cells in the initial received packets. Then, so-called Presentation/Decode Time Stamps (PTS/DTS) included in the audio and video data are advantageously employed in conjunction with STC to display properly the received data. Invention, underflow of the receiver data buffers is alleviated by the addition of a 'jitter-delay (D.sub.j)' value which causes an extra accumulation of data in the data buffers prior to decoding. Dynamic tracking of the jitter-delay of the channel is obtained by monitoring the fullness of the data buffers and controllably adjusting the jitter-delay, accordingly. The stability of the decoder video timing is enhanced by employing an additional phase locked loop in a video display control which is supplied with a timing error signal. The additional phase locked loop includes a switch, filter, clipper and voltage controlled oscillator (VCO). The switch is enabled in response to output pulses from the VCO to supply the instantaneous error signal input to the filter for each so-called video presentation unit. The VCO has a very stable center frequency which variation is limited by clipping an input control voltage to some small voltage range. Output pulses from the VCO are employed to enable decoding of the presentation units. Faster synchronization is provided at start-up by increasing, via control of the clipper, the allowable voltage range of the VCO.

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First Claim