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Abstract

A parallel processing architecture of run length codes in an image processing system wherein the run-length codes are represented by the run-start addresses and the run-end addresses of black runs. The image data is loaded into this processing architecture by unit of words. A run detector in the parallel processing architecture detects if there are run-start or run-end bits in a word. When there are run-start bits or run-end bits present in a word, this parallel architecture employs a run-start row address generator and a run-end row address generator, which are all logic circuits and comprise a data flow hardware architecture, to generate run-start row addresses and run-end row addresses in parallel without the CPU intervening. A ripple counter is utilized to derive the crossing count parameter by counting the total number of black runs in a row of image data.

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