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Abstract

A data transfer controller for controlling DMA data transfer between a memory area and a peripheral unit. The data transfer controller has a first register which stores address information relative to a predetermined address of the memory area. A DMA control unit uses the first register and a second register to perform the DMA data transfer between the memory area and the peripheral unit. The data transfer controller also has a third register for storing data used for accessing the memory area of the DMA transfer. An updater is used to update the contents of the third register whenever a memory access uses the third register and is different from a memory access associated with data transfer between the memory area and the peripheral unit. Finally, a counter changes the contents of the third register in one direction whenever the data transfer between the memory area and the peripheral unit is performed. The counter changes the contents of the third register in an opposite direction whenever memory access using the third register is performed.

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