Automatic cache flush with readable and writable cache tag memory
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United States of America Patent
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Feb 15, 1994
Issued Date -
N/A
app pub date -
May 4, 1992
filing date -
Dec 19, 1991
priority date (Note) -
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status (Latency Note)
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Abstract
According to the invention, a chipset is provided which powers up in a default state with cacheing disabled and which writes permanently non-cacheable tags into tag RAM entries corresponding to memory addresses being read while cacheing is disabled. Even though no 'valid' bit is cleared, erroneous cache hits after cacheing is enabled are automatically prevented since any address which does match a tag in the tag RAM, is a non-cacheable address and will force retrieval directly from main memory anyway. Two cache tag test modes are also described, as is a cache sizing algorithm.
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