Duo-binary and/or binary data slicer
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United States of America Patent
Stats
-
Feb 22, 1994
Grant Date -
N/A
app pub date -
Feb 19, 1992
filing date -
Feb 21, 1991
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A duo-binary and/or binary data slicer has a data input (10) coupled via a capacitor (C1) to a d.c. restoring circuit (A2 to Q6 and Q9 to Q13) d.c. reference level is superimposed on the data signal. A sample and hold circuit (C2, Q15 to Q22) is arranged to sample the data signal and provide a voltage related to the upper and lower peak value. A divider (R16-R19) is coupled between the d.c. reference level and the voltage related to the upper and lower peak value and provides intermediate output voltages (DU, DL, B) relating to duo-binary and/or binary level for determining the slicing levels.
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