Importance

Loading Importance Indicators...

Abstract

An I/O interface controller is disclosed which can be programmed to interact with a variety of interface protocols. The host side and the peripheral side of the interface controller are independently programmable. All significant operations are performed in a single chip gate array. The gate array includes registers for establishing control with peripheral devices and for transferring data between peripheral devices and the host. An arithmetic logic unit is used for calculation and data manipulation while an I/O operation is occurring. A condition code multiplexer evaluates the contents of registers within the single chip and instructs the sequencer to perform various operations based on these results. Strobe signals from a peripheral device, indicating that valid data is ready to be transferred, are quickly acknowledged by virtue of an asynchronous signal path. The strobe signal is also processed so that it may correspond with the internal clock of the I/O interface. An asynchronous event driver and recognizer mechanism is also disclosed. This mechanism enable the I/O interface controller to drive the host side and the peripheral side interfaces simultaneously.

Loading the Abstract Image...

First Claim