Importance

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Abstract

At least two double buffers or FIFOs, each FIFO including a first group of latches in series with a second group of latches, coupled between a host data bus and a corresponding bank or way of interleaved memory. The inputs of the first group of latches are coupled to the host data bus, and the inputs of the second group of latches are coupled to the outputs of the first group of latches of each double buffer or FIFO. The outputs of the second group of latches are coupled to the memory data bus of the corresponding way of interleaved memory. During a burst write sequence, an address is placed on the host address bus and a series of data doublewords are sequentially placed onto the host data bus, while the DRAMs of main memory are entering into page mode. The first group of latches of each double buffer or FIFO latches in every other data doubleword. The second level of latches stores the data from the corresponding first level of latches to provide the data to the DRAMs according to the timing requirements of the DRAMs. In this manner, the CPU or cache controller providing data to the host bus may operate at full speed without inserting wait states while the DRAMs enter into page mode.

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First Claim