Method of logic circuit simulation
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United States of America Patent
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Mar 8, 1994
Grant Date -
N/A
app pub date -
Jun 21, 1991
filing date -
Jun 25, 1990
priority date (Note) -
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Abstract
A method of logic simulation includes the steps of reading delay time of a logic element itself calculated in advance, converting output logic value of the logic element to a voltage value, forming a circuit equation based on connection information of an output impedance circuit of the logic element, calculating a voltage value at an arbitrary node of the output impedance circuit by solving the circuit equation, and converting a voltage value of an input node of a logic element of the succeeding stage to a logic value.
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