Preemption control for central processor with cache
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United States of America Patent
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-
Mar 8, 1994
Grant Date -
N/A
app pub date -
Oct 27, 1989
filing date -
Oct 27, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A logic controlled gate is inserted in the arbitration logic of a computer system that supports multiple masters on a data bus. In such a system with arbitration for data bus ownership, the gate is so controlled that competitors for the data bus cannot force the main processor (CPU) from the data bus until certain system conditions are met. In particular, a pattern of CPU 'hits' to memory cache is recognized as an opportunity for the CPU to relinquish the data bus.
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