Importance

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Abstract

A field synchronization system for asynchronous video signals, comprises a video display synchronized with a first video signal having a first line rate component and a first field rate component. A second video signal having a second line rate component is first stored in a field memory, having synchronous write and read ports. The second video signal is thereafter speeded up in a multiple line memory having asynchronous write and read ports and independently resettable write and read pointers. The second video signal may be subsampled, written and read into and out of the field memory respectively and written into the multiple line memory, all synchronously with the second line rate component. The second video signal is read out of the multiple line memory synchronously with the first line rate component. The write pointer is reset by a circuit which samples the first field rate component with the second line rate component. The read pointer is reset by a circuit which samples the first field rate component with the first line rate component. A delay circuit ensures that the write pointer is reset at the first end of a line period of the second video signal after every start of field of the first video signal and ensures that the read pointer is reset at the second end of a line period of the first video signal after the resetting of the write pointer.

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First Claim