Apparatus for providing a system clock locked to an external clock over a wide range of frequencies
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United States of America Patent
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Mar 15, 1994
Grant Date -
N/A
app pub date -
Dec 23, 1991
filing date -
Dec 23, 1991
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A digital phase lock loop circuit for synchronizing the phase of clock signals delivered to devices through clock tree circuitry with the phase of input clock signals including a first delay line, a second delay line, a phase detector circuit, apparatus for transferring the input clock signals through the first delay line to the phase detector circuit, apparatus for transferring the input clock signals through the second delay line and the clock tree circuitry to the phase detector circuit, apparatus responsive to the difference in phase detected between the clock signals transferred through the first and second delay lines for varying the delay of one of the delay lines to bring the clock signals transferred through the first and second delay lines into phase with one another.
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