Importance

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Abstract

A method and apparatus for programming a mass storage device of the type having a plurality of memory word locations. The memory word locations are organized into a plurality of addressable columns and addressable rows, each memory word location capable of storing one byte word in response to at least two programming steps. Each programming step for a selected memory word location requires a predetermined time period before a subsequent programming step can be processed by the selected memory word location. A first programming step is applied to a first memory word location. The first programming step is applied sequentially to other memory word locations while the first programming step is being processed by the first memory word location. A second programming step is applied to the first memory word location while the first programming step is being process by the other memory word locations. The second programming step is sequentially applied to the other memory word locations while the second programming step is being processed by the first memory word location. Also disclosed is a method of erasing such memory and a method for storing and processing bad address locations.

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First Claim