Method of making two-phase buried channel planar gate CCD
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United States of America Patent
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Mar 29, 1994
Grant Date -
N/A
app pub date -
Dec 18, 1992
filing date -
Dec 18, 1992
priority date (Note) -
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Abstract
The present invention is directed to a method of making a true two-phase CCD using a single layer (level) of the conductive material for the gate electrodes to provide a planar structure. The method includes using L-shaped masking layers having a submicron length of a bottom portion between two masking layers of silicon dioxide on and spaced along a surface of a conductive layer. The conductive layer is over and insulated from a surface of a body of a semiconductor material having a channel region therein. The L-shaped masking layers are removed to expose a spaced narrow portions of the conductive layer. The conductive layer is then etched completely therethrough at each exposed portion to divide the conductive layer into gate electrodes which are spaced apart by submicron width gaps.
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