Versatile and efficient cell-to-local bus interface in a configurable logic array
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United States of America Patent
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Mar 29, 1994
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app pub date -
Apr 8, 1993
filing date -
Aug 29, 1991
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Abstract
A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.
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