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Abstract

An ECL circuit with power control is disclosed. The ECL circuit comprises a pair of emitter-coupled transistors with a current source transistor having its collector coupled to the coupled-emitters of the pair. Coupled in series with the base of the current source transistor is a first MOS transistor with its gate receiving an enable signal to control the first MOS transistor. As such, an activated first MOS transistor switches on the ECL circuit, and a de-activated first MOS transistor switches off the ECL circuit with no current through the current source transistor to provide a true power down of the ECL circuit. An ECL circuit for translating from CMOS to ECL levels is also disclosed. The ECL circuit comprises a pair of emitter-coupled transistors and first MOS transistor coupled in series with a first base of the pair at one end of the source/drain current path of the first MOS transistor. Another end of the source/drain current path of the first MOS transistor is coupled to a current-source voltage, while its gate receives an enable signal. Coupled in series with a second base of the pair at one end of the source/drain current path of the second MOS transistor is a second MOS transistor. Another end of the source/drain current path of the second MOS transistor is also coupled to the current-source voltage, while its gate receives an inverted enable signal. Thus, the pair has its two emitter-coupled transistors alternately switched on by the enable and inverted enable signals. An ECL circuit for multiplexing ECL inputs with CMOS select signals is further disclosed. The ECL circuit comprises the top portion of a conventional ECL multiplexer connected to a pair of Vcs current sources. The current sources are alternately selected by the N-channel MOS transistor coupled between the Vcs current source and one base of the n-p-n transistors.

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First Claim