CMOS low power mixed voltage bidirectional I/O buffer
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United States of America Patent
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Apr 5, 1994
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N/A
app pub date -
Feb 10, 1993
filing date -
Feb 10, 1993
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Abstract
This invention describes the design and implementation of a low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the highest logic level signals to drive the final output stage which outputs a selectable logic level signal. The invention further translates input signals of a variety of logic levels into low voltage core logic level signals. In either case, AC and DC power consumption is minimized in a mixed power supply environment that requires voltage translation to represent the proper binary logic levels.
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