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Abstract

Two memory cells are formed adjacent each other on a semiconductor substrate. In each memory cell, eight MOS transistors are formed between two selection transistors such that the MOS transistors and the selection transistors are connected in series, and that a source/drain diffusion layer is shared by adjacent ones of the selection transistors and the MOS transistors. A drain layer is shared by two adjacent selection transistors of the two memory cells. Ferroelectric capacitors are formed on the respective MOS transistors. A common electrode serves both as a gate electrode of the MOS transistor and a bottom electrode of the ferroelectric capacitor. Gate electrodes of the selection transistors, the common electrodes, and top electrodes of the ferroelectric capacitors are connected to word lines, and the above drain diffusion layer is connected to a bit line.

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First Claim