Performance lateral double-diffused MOS transistor

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United States of America Patent

PATENT NO 5304827
SERIAL NO

07976713

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Abstract

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A transistor has a JFET gate region of a first conductivity type formed at the face of a semiconductor layer to laterally and downwardly surround a drift region of a second conductivity type. A thick insulator region is formed on a portion of the drift region at the face. A IGFET body of the first conductivity type is formed at the face to be adjacent the JFET gate region. This body spaces a source region of the second conductivity type from the drift region. A drain region is formed at the face to be of the second conductivity type and to adjoin the drift region, and to be spaced from the IGFET body. A conductive gate extends over the face between the source region and the thick insulator region, with a thin gate insulator spacing the gate from the IGFET body. The enhanced doping concentration of the JFET gate region with respect to the semiconductor layer allows the dopant concentration of the drift region to likewise be increased, thereby allowing RESURF conditions to be met at the rated voltage and with a lower r.sub.ds (on).

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Patent Owner(s)

Patent OwnerAddress
TEXAS INSTRUMENTS INCORPORATEDDALLAS TX

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Malhi, Satwinder Garland, TX 68 3351
Ng, Wai T Plano, TX 6 183

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