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Abstract

A parallel processor has a plurality of communication buses advantageously interconnecting the arithmetic processor elements, the memory controller elements, a global controller circuitry, and input/output processors. The processor preferably has at least one central processing unit cluster, the cluster having at least one integer processor and one floating point processor. A plurality of I/F buses interconnect the integer and floating point processors of a cluster for communications therebetween. Integer load buses connect the integer processors of each cluster and selectively connect those processors to the memory controllers for transferring data from memory to the clusters and for providing inter-integer processor data communications. A plurality of floating point load buses connect the floating point processors of the clusters to selected memory controllers for transferring data from the controllers to the floating point processors and for providing inter-floating point processor data communications. A plurality of physical address buses provide one-way communications for transferring memory addresses from the integer processors to the memories and a plurality of storage buses connect the floating point processors to the memory controllers along a one-way communications path for transferring data to be stored in the memories. The hardware architecture provides advantageous communications between the elements of the data processing system for enabling wide bandwidth communications and high instruction throughput.

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