Importance

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Abstract

A binary shifter which utilizes shifter control logic to shift a 64-bit binary word by shift amounts up to 63 bit positions using a pre-multiplexer and shifter array configuration capable of shifting up to 32 bit positions. The shifter control logic executes two cycles of shifting operations to achieve shift amounts greater than 32 bits. An improved shifter pre-multiplexer and array for shifting 64-bit binary words by up to 32 bit positions in one cycle is disclosed. The improved shifter pre-multiplexer and array uses 9:1 pre-multiplexer cells with tristate outputs to place input data on selected discrete sections of horizontal data lines allowing for a reduced number of cells and control lines.

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First Claim