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Abstract

An antifuse memory cell having a P.sup.+ polysilicon doping in a region directly under an intrinsic silicon programming layer. The P.sup.+ polysilicon region is surrounded by an N.sup.- polysilicon doped region, and the two regions are sandwiched between layers of silicon dioxide insulation. The interface between the two regions is a P-N junction, in fact, a diode. The diode does not suffer from a diffusion current that increases with increasing levels of N.sup.- doping, therefore the N.sup.-polysilicon can be heavily doped to yield a very conductive bit line interconnect for a memory matrix. The interconnect line widths can be very narrow, and further microminiaturization is aided thereby. The top metalization is aluminum and serves as a word line interconnect in the memory matrix.

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First Claim