Low power, high performance PLA
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United States of America Patent
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-
May 10, 1994
Grant Date -
N/A
app pub date -
Dec 17, 1992
filing date -
Dec 17, 1992
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A programmable logic array (PLA) is provided with a decoder at the input. Each product term line of the PLA has an associated power switch that is controlled by an output of the decoder. Only a portion of the PLA that includes the product term lines activated for a particular operation is powered up for that operation, thus minimizing power consumption.
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