Stacked chip assembly and manufacturing method therefor

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5311401
SERIAL NO

07727500

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ATTORNEY / AGENT: (SPONSORED)

Importance

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Abstract

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Two or more integrated circuit or memory chips (64-66, 104, 106-108, 116-118, 122-126) are stacked on a circuit substrate (72, 100) or a printed-wiring board in such a manner that the planes of the chips lie horizontally, rather than vertically, on the substrate or wiring board. The chips are preferably interconnected along all of their edges (68) and thence, preferably by ribbon bonds, to the substrate or wiring board. The thus assembled arrangement is hermetically sealed by coatings of passivation and encapsulant. Such chips (25) are oversized, as distinguished from chips conventionally diced from wafers. Specifically, each chip is larger than an individual wafer circuit (18, 20), that is, each wafer portion (24) which is selected to be formed into a chip has a size that is larger than the individual wafer circuit which it incorporates, thus overlapping adjacent circuits.

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Patent Owner(s)

Patent OwnerAddress
RAYTHEON COMPANY1100 WILSON BLVD ARLINGTON VA 22209

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cochran, Richard K Ingelwood, CA 1 141
Gates, Jr Louis E Westlake Village, CA 12 462

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