Synchronous type semiconductor memory
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United States of America Patent
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May 10, 1994
Grant Date -
N/A
app pub date -
Apr 12, 1993
filing date -
Nov 20, 1990
priority date (Note) -
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Abstract
A DRAM is capable of regulating an output timing of a read data. The output timing of the read data can be regulated by the DRAM which has a circuit (127) for counting the number of clock pulses until the read data is transferred to a data latch circuit (121) and a circuit (129) for outputting the counted number. The DRAM has a circuit (125) which can regulate the output timing in response to an external input signal.
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