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Abstract

A FPGA matching the organization and performance of mask programmable gate arrays is presented. The core array is organized into rows of continuous series transistors (CSTs) and rows of small latch/logic blocks. The source/drains and gate of each of the transistors are connected to line segments. The input and output terminals of the blocks are also connected to line segments. Programmable antifuses are located at the intersections of the line segments, which also include others for power and routing purposes. The FPGA can be efficiently configured into a user's application with the flexibility of the CSTs and the efficiency of the latch/logic blocks, which may also be configured into RAM arrays.

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First Claim