Apparatus and method for preventing I/O bandwidth limitations in fast fourier transform processors
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United States of America Patent
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May 17, 1994
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Mar 8, 1993
filing date -
Apr 18, 1991
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Abstract
A Quasi Radix-16 Butterfly comprises an radix-4 butterfly processor and on-board memory with external memory addressing changes from a conventional radix-4 butterfly processor. On-chip cache memory is included to store data outputs of the radix-4 butterfly processor for application as data inputs to the radix-4 butterfly processor in a second series of butterfly operations to implement high-speed processing that is maximally execution-bound.
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