One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture
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United States of America Patent
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May 24, 1994
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N/A
app pub date -
Mar 12, 1993
filing date -
Mar 12, 1993
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Abstract
There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use 'zero power' during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.
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