Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle
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United States of America Patent
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May 31, 1994
Grant Date -
N/A
app pub date -
May 28, 1992
filing date -
May 28, 1992
priority date (Note) -
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Abstract
In an integrated circuit for synthesizing a 50% duty cycle internal clock, the internal clock is synchronized with zero phase difference with respect to an external reference clock having the same frequency. The duty cycle of the synthesized waveform is fixed and invariant with respect to the reference clock duty cycle. Synchronization of the two clocks is achieved by a delay-line-loop using an inverting voltage controlled delay line with a nominal half period delay. The 50% duty cycle is achieved by a second control loop that has as its input both the reference and synthesized clock. This second loop also shares the voltage controlled delay line with the delay-line-loop.
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