Importance

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Abstract

The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of rows of logic cells and a plurality of columns of logic cells. The array further includes at least one horizontally aligned local bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned local bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array also includes means for configuring the array such that any logic cell A in the array can write to a local bus which can be linked through the array's bussing network so that logic cell A can be read by any other logic cell B; correspondingly, logic cell B can write to a local bus which is linked through the same components such that data written by logic cell B can be read by logic cell A. Whether a logic element is reading from or writing to a local bus in controlled by a logic function created in the array. The configuration capability is due to means for placing the bus drivers in a high impedance state, means for bidirectional bussing capability due to extra passgates in the array repeaters, and means for connecting horizontal busses to vertical busses through the use of a core cell to bus interface.

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First Claim