Apparatus and method for TLB purge reduction in a multi-level machine system

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United States of America Patent

PATENT NO 5317705
SERIAL NO

08112174

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Abstract

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A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machine, or an underlying guest machine. A system for reducing the number of cases in which guest translations are based on host page table entries is provided. Additional logic is supplied to analyze each invalidate page table entry (IPTE) instruction to minimize the extent of purging required as a result of that instruction. When the region relocate facility is in operation, or when no pageable TLB's have been constructed, only the entry corresponding to the page table entry to be invalidated need be purged. This limited purging reduces the overhead by reducing the time spent in purging and the time required in address translation to rebuild the TLB. This time saving results in increased performance in systems with multi-level guests.

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Patent Owner(s)

Patent OwnerAddress
INTERNATIONAL BUSINESS MACHINES CORPORATIONARMONK NEW YORK 10504

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gannon, Patrick M Poughkeepsie, NY 4 414
Gum, Peter H Poughkeepsie, NY 11 1305
Hough, Roger E Highland, NY 16 1794
Murray, Robert E Woodstock, NY 8 826

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