VGA controlled having frame buffer memory arbitration and method therefor
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United States of America Patent
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-
Jun 7, 1994
Grant Date -
N/A
app pub date -
Jun 22, 1992
filing date -
Jun 22, 1992
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An improved VGA Controller with Arbitration Logic and method therefor is provided to enhance system performance by efficiently using the minimum amount of bus bandwidth required. This Controller includes a bus to the Frame Buffer that either the system CPU or the Display Controller may access and control. The Display Controller includes a Display FIFO which stores display data from the Frame Buffer for the Display Controller to use. This Display FIFO coupled with the Arbitration Logic makes it possible for the Display Controller to continue to output display data even when the system CPU is accessing the display data in the Frame Buffer. The Arbitration Logic attempts to keep the Display FIFO as full as possible such that a bus request by the system CPU can be immediately granted when received.
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