US Patent No: 5,319,755

Number of patents in Portfolio can not be more than 2000

Integrated circuit I/O using high performance bus interface

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ATTORNEY / AGENT: (SPONSORED)
 

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Abstract

An apparatus for storing and retrieving data is described. The apparatus includes a circuitry for initiating data transmission, a first memory, a second memory, and a multiline bus for transferring control information, addresses, and the data. The control information includes information for selecting one of the first and second memories without using any separate memory select line. Configuration circuitry is provided for assigning a first identification value to the first memory and a second identification value to the second memory. The configuration circuitry includes a first reset line for coupling the circuitry for initiating data transmission to the first memory, a second reset line for coupling the first memory to the second memory, a first identification register for the first memory, a second identification register for the second memory, circuitry for generating a first reset signal and a second reset signal and for sending the first and second reset signals to the first identification register, circuitry for propagating the first and second reset signals from the first identification register to the second identification register, circuitry for resetting the first and second identification registers in response to the first reset signal, and circuitry for setting the first identification register to the first identification value and the second identification register to the second identification value in response to the second reset signal.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
RAMBUS INC.LOS ALTOS, CA1206

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farmwald, Michael Berkeley, CA 59 3714
Horowitz, Mark Menlo Park, CA 79 3779

Cited Art

Patent Info (Count) # Cites Year
 
TEXAS INSTRUMENTS INCORPORATED (4)
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NCR CORPORATION (2)
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DATAPOINT CORPORATION (1)
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IRVINE SENSORS CORPORATION (1)
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KABUSHIKI KAISHA TOSHIBA (1)
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LORAL AEROSPACE CORP. A CORPORATION OF DE (1)
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MIPS TECHNOLOGIES, INC. (1)
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MOTOROLA, INC. (1)
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NEC CORPORATION (1)
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XEROX CORPORATION (1)
5,023,488 Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines 193 1990
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (3)
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Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (72)
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7,133,972 Memory hub with internal cache and/or memory access prediction 86 2002
7,149,874 Memory hub bypass circuit and method 9 2002
6,842,393 Method for selecting one or a bank of memory devices 4 2002
7,245,145 Memory module and method having improved signal routing topology 10 2003
7,120,727 Reconfigurable memory module and method 113 2003
7,428,644 System and method for selective memory module power management 43 2003
7,260,685 Memory hub and access method having internal prefetch buffers 31 2003
7,107,415 Posted write buffers and methods of posting write requests in memory modules 21 2003
7,389,364 Apparatus and method for direct memory access in a hub-based memory system 2 2003
7,210,059 System and method for on-board diagnostics of memory modules 66 2003
7,133,991 Method and system for capturing and bypassing memory transactions in a hub-based memory system 11 2003
7,136,958 Multiple processor system and method including multiple memory hub modules 31 2003
7,310,752 System and method for on-board timing margin testing of memory modules 5 2003
7,194,593 Memory hub with integrated non-volatile memory 36 2003
7,120,743 Arbitration system and method for memory responses in a hub-based memory system 47 2003
7,181,584 Dynamic command and/or address mirroring system and method for memory modules 36 2004
7,120,723 System and method for memory hub-based expansion bus 23 2004
7,213,082 Memory hub and method for providing memory sequencing hints 17 2004
6,980,042 Delay line synchronizer apparatus and method 45 2004
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7,180,522 Apparatus and method for distributed memory control in a graphics processing system 5 2004
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7,249,236 Method and system for controlling memory accesses to memory modules having a memory hub architecture 3 2004
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7,222,197 Apparatus and method for direct memory access in a hub-based memory system 3 2005
7,282,947 Memory module and method having improved signal routing topology 8 2005
7,605,631 Delay line synchronizer apparatus and method 4 2005
7,415,567 Memory hub bypass circuit and method 2 2006
7,222,210 System and method for memory hub-based expansion bus 6 2006
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7,174,409 System and method for memory hub-based expansion bus 7 2006
7,418,526 Memory hub and method for providing memory sequencing hints 25 2006
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7,251,714 Method and system for capturing and bypassing memory transactions in a hub-based memory system 6 2006
7,689,879 System and method for on-board timing margin testing of memory modules 4 2006
7,529,896 Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules 1 2006
7,437,579 System and method for selective memory module power management 37 2006
7,278,060 System and method for on-board diagnostics of memory modules 2 2006
7,412,566 Memory hub and access method having internal prefetch buffers 14 2006
7,386,649 Multiple processor system and method including multiple memory hub modules 15 2006
7,353,320 Memory hub and method for memory sequencing 2 2006
7,644,253 Memory hub with internal cache and/or memory access prediction 1 2006
7,546,435 Dynamic command and/or address mirroring system and method for memory modules 0 2007
7,370,134 System and method for memory hub-based expansion bus 23 2007
7,716,444 Method and system for controlling memory accesses to memory modules having a memory hub architecture 3 2007
7,516,363 System and method for on-board diagnostics of memory modules 4 2007
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7,581,055 Multiple processor system and method including multiple memory hub modules 3 2007
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7,610,430 System and method for memory hub-based expansion bus 9 2008
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7,913,122 System and method for on-board diagnostics of memory modules 0 2008
7,945,737 Memory hub with internal cache and/or memory access prediction 0 2009
7,975,122 Memory hub with integrated non-volatile memory 0 2009
7,746,095 Memory module and method having improved signal routing topology 2 2009
7,873,775 Multiple processor system and method including multiple memory hub modules 0 2009
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7,958,412 System and method for on-board timing margin testing of memory modules 3 2010
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8,117,371 System and method for memory hub-based expansion bus 0 2011
8,234,479 System for controlling memory accesses to memory modules having a memory hub architecture 0 2011
 
RAMBUS INC. (55)
6,035,369 Method and apparatus for providing a memory with write enable information 33 1995
5,715,407 Process and apparatus for collision detection on a parallel bus by monitoring a first line of the bus during even bus cycles for indications of overlapping packets 21 1996
5,765,020 Method of transferring data by transmitting lower order and upper odermemory address bits in separate words with respective op codes and start information 21 1997
5,896,545 Transmitting memory requests for multiple block format memory operations the requests comprising count information, a mask, and a second mask 27 1997
5,872,996 Method and apparatus for transmitting memory requests by transmitting portions of count data in adjacent words of a packet 72 1997
6,810,449 Protocol for communication with dynamic memory 31 2000
6,266,737 Method and apparatus for providing a memory with write enable information 41 2000
RE39879 Method of transferring data by transmitting lower order and upper order memory address bits in separate words with respective op codes and start information 0 2000
6,591,353 Protocol for communication with dynamic memory 33 2000
6,369,652 Differential amplifiers with current and resistance compensation elements for balanced output 34 2000
6,542,976 Memory device having an internal register 15 2000
6,405,296 Asynchronous request/synchronous data dynamic random access memory 8 2000
6,532,522 Asynchronous request/synchronous data dynamic random access memory 7 2000
6,496,897 Semiconductor memory device which receives write masking information 75 2001
6,470,405 Protocol for communication with dynamic memory 37 2001
6,806,728 Circuit and method for interfacing to a bus channel 32 2001
6,493,789 Memory device which receives write masking and automatic precharge information 79 2001
7,484,064 Method and apparatus for signaling between devices of a memory system 8 2001
6,931,467 Memory integrated circuit device which samples data upon detection of a strobe signal 20 2002
6,681,288 Memory device with receives write masking information 34 2002
7,085,906 Memory device 2 2002
6,861,884 Phase synchronization for wide area integrated circuits 4 2003
7,225,311 Method and apparatus for coordinating memory operations among diversely-located memory components 8 2003
7,301,831 Memory systems with variable delays for write data signals 10 2004
7,161,400 Phase synchronization for wide area integrated circuits 0 2004
7,287,109 Method of controlling a memory device having a memory core 14 2004
7,197,611 Integrated circuit memory device having write latency function 17 2005
7,209,397 Memory device with clock multiplier circuit 9 2005
7,225,292 Memory module with termination component 8 2005
7,200,055 Memory module with termination component 7 2005
8,391,039 Memory module with termination component 0 2005
7,210,016 Method, system and memory controller utilizing adjustable write data delay settings 10 2005
7,177,998 Method, system and memory controller utilizing adjustable read data delay settings 10 2006
7,932,755 Phase synchronization for wide area integrated circuits 0 2007
7,360,050 Integrated circuit memory device having delayed write capability 3 2007
7,287,119 Integrated circuit memory device with delayed write command processing 11 2007
7,330,952 Integrated circuit memory device having delayed write timing based on read response time 4 2007
7,330,953 Memory system having delayed write timing 3 2007
7,437,527 Memory device with delayed issuance of internal write command 0 2007
7,315,929 Memory device 1 2007
7,480,193 Memory component with multiple delayed timing signals 5 2007
8,214,616 Memory controller device having timing offset capability 2007
8,320,202 Clocked memory system with termination component 0 2007
7,496,709 Integrated circuit memory device having delayed write timing based on read response time 3 2007
7,870,357 Memory system and method for two step memory write operations 1 2008
7,724,590 Memory controller with multiple delayed timing signals 5 2008
7,793,039 Interface for a semiconductor memory device and method for controlling the interface 0 2009
8,359,445 Method and apparatus for signaling between devices of a memory system 0 2009
8,045,407 Memory-write timing calibration including generation of multiple delayed timing signals 0 2010
8,019,958 Memory write signaling and methods thereof 0 2010
8,140,805 Memory component having write operation with multiple time periods 0 2010
8,218,382 Memory component having a write-timing calibration mode 0 2011
8,205,056 Memory controller for controlling write signaling 0 2011
8,395,951 Memory controller 0 2012
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MICRON TECHNOLOGY, INC. (54)
6,453,377 Computer including optical interconnect, memory unit, and method of assembling a computer 52 1998
7,941,056 Optical interconnect in high-speed memory systems 2 2001
6,519,658 Memory unit and method of assembling a computer 14 2002
6,715,018 Computer including installable and removable cards, optical interconnection between cards, and method of assembling a computer 108 2002
7,200,024 System and method for optically interconnecting memory devices 22 2002
7,117,316 Memory hub and access method having internal row caching 14 2002
7,254,331 System and method for multiple bit optical data transmission in memory systems 10 2002
6,944,743 Memory hub bypass circuit and method 0 2002
7,836,252 System and method for optimizing interconnections of memory devices in a multichip module 1 2002
6,662,243 Memory unit, a method of assembling a memory unit, a method of reconfiguring a system, and a memory device 0 2003
6,937,057 Memory module and method having improved signal routing topology 0 2003
7,366,920 System and method for selective memory module power management 0 2003
6,952,744 Computer including optical interconnect, memory unit, and method of assembling a computer 2 2003
7,234,070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 13 2003
7,137,024 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 0 2003
7,330,992 System and method for read synchronization of memory modules 4 2003
7,188,219 Buffer control system and method for a memory system having outstanding read and write request buffers 34 2004
7,788,451 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 10 2004
7,412,574 System and method for arbitration of memory responses in a hub-based memory system 14 2004
7,257,683 Memory arbitration system and method having an arbitration packet protocol 7 2004
7,447,240 Method and system for synchronizing communications links in a hub-based memory system 3 2004
7,590,797 System and method for optimizing interconnections of components in a multichip memory module 1 2004
7,222,213 System and method for communicating the synchronization status of memory modules during initialization of the memory modules 31 2004
7,363,419 Method and system for terminating write commands in a hub-based memory system 30 2004
7,519,788 System and method for an asynchronous data buffer having buffer write and read pointers 4 2004
7,310,748 Memory hub tester interface and method for use thereof 9 2004
7,106,611 Wavelength division multiplexed memory module, memory system and method 20 2004
7,392,331 System and method for transmitting data packets in a computer system having a memory hub architecture 7 2004
7,289,347 System and method for optically interconnecting memory devices 7 2005
7,301,838 Sense amplifier circuitry and architecture to write data into and/or read from memory cells 45 2005
7,272,682 Memory hub bypass circuit and method 0 2006
7,870,329 System and method for optimizing interconnections of components in a multichip memory module 2 2006
7,594,088 System and method for an asynchronous data buffer having buffer write and read pointers 1 2006
7,805,586 System and method for optimizing interconnections of memory devices in a multichip module 2 2006
7,596,641 System and method for transmitting data packets in a computer system having a memory hub architecture 1 2006
7,489,875 System and method for multiple bit optical data transmission in memory systems 1 2006
7,434,081 System and method for read synchronization of memory modules 1 2006
7,266,633 System and method for communicating the synchronization status of memory modules during initialization of the memory modules 8 2006
7,529,273 Method and system for synchronizing communications links in a hub-based memory system 3 2006
7,461,286 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 5 2006
7,411,807 System and method for optically interconnecting memory devices 2 2006
7,382,639 System and method for optically interconnecting memory devices 1 2006
7,412,571 Memory arbitration system and method having an arbitration packet protocol 7 2007
7,823,024 Memory hub tester interface and method for use thereof 1 2007
7,774,559 Method and system for terminating write commands in a hub-based memory system 9 2007
7,486,563 Sense amplifier circuitry and architecture to write data into and/or read from memory cells 23 2007
8,082,404 Memory arbitration system and method having an arbitration packet protocol 0 2008
8,392,686 System and method for read synchronization of memory modules 0 2008
7,949,803 System and method for transmitting data packets in a computer system having a memory hub architecture 0 2009
8,239,607 System and method for an asynchronous data buffer having buffer write and read pointers 0 2009
8,291,173 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 0 2010
8,190,819 System and method for optimizing interconnections of memory devices in a multichip module 0 2010
8,438,329 System and method for optimizing interconnections of components in a multichip memory module 0 2011
8,346,998 System and method for transmitting data packets in a computer system having a memory hub architecture 0 2011
 
TEXAS INSTRUMENTS INCORPORATED (24)
5,636,176 Synchronous DRAM responsive to first and second clock signals 12 1994
6,188,635 Process of synchronously writing data to a dynamic random access memory array 0 1995
5,805,518 Memory circuit accommodating both serial and random access, having a synchronous DRAM device for writing and reading data 5 1995
5,768,205 Process of transfering streams of data to and from a random access memory device 1 1995
5,684,753 Synchronous data transfer system 24 1995
5,680,358 System transferring streams of data 2 1995
5,680,367 Process for controlling writing data to a DRAM array 0 1995
5,680,368 Dram system with control data 0 1995
5,680,369 Synchronous dynamic random access memory device 1 1995
5,680,370 Synchronous DRAM device having a control data buffer 1 1995
5,587,962 Memory circuit accommodating both serial and random access including an alternate address buffer register 9 1995
6,418,078 Synchronous DRAM device having a control data buffer 2 2000
6,662,291 Synchronous DRAM System with control data 3 2002
6,728,828 Synchronous data transfer system 2 2003
6,738,860 Synchronous DRAM with control data buffer 0 2003
6,735,667 Synchronous data system with control data buffer 2 2003
6,732,224 System with control data buffer for transferring streams of data 2 2003
6,728,829 Synchronous DRAM system with control data 1 2003
6,910,096 SDRAM with command decoder coupled to address registers 2 2003
6,748,483 Process of operating a DRAM system 0 2003
6,735,668 Process of using a DRAM with address control data 0 2003
6,732,225 Process for controlling reading data from a DRAM array 0 2003
6,732,226 Memory device for transferring streams of data 0 2003
6,895,465 SDRAM with command decoder, address registers, multiplexer, and sequencer 2 2004
 
MOSAID TECHNOLOGIES INCORPORATED (13)
6,510,503 High bandwidth memory interface 168 1998
6,779,097 High bandwidth memory interface 44 2002
6,657,918 Delayed locked loop implementation in a synchronous dynamic random access memory 39 2002
6,657,919 Delayed locked loop implementation in a synchronous dynamic random access memory 40 2003
6,992,950 Delay locked loop implementation in a synchronous dynamic random access memory 37 2003
7,299,330 High bandwidth memory interface 35 2004
7,599,246 Delay locked loop implementation in a synchronous dynamic random access memory 0 2005
7,535,749 Dynamic memory word line driver scheme 0 2006
8,266,372 High bandwidth memory interface 0 2007
8,250,297 High bandwidth memory interface 0 2007
7,765,376 Apparatuses for synchronous transfer of information 0 2007
8,023,314 Dynamic memory word line driver scheme 0 2009
8,369,182 Delay locked loop implementation in a synchronous dynamic random access memory 0 2009
 
JAZIO, INC. (10)
6,160,423 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 117 1998
6,151,648 High speed bus system and method for using voltage and timing oscillating references for signal detection 78 1998
6,255,859 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 57 1999
6,327,205 Signal latching of high bandwidth DRAM arrays when skew between different components is higher than signal rate 58 2000
6,513,080 High speed bus system and method for using voltage and timing oscillating references for signal detection 52 2000
6,812,767 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 1 2001
7,123,660 Method and system for deskewing parallel bus channels to increase data transfer rates 8 2002
7,009,428 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 0 2004
7,190,192 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 0 2005
7,126,383 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 0 2005
 
INTELLECTUAL VENTURES II LLC (8)
5,537,353 Low pin count-wide memory devices and systems and methods using the same 11 1995
5,636,174 Fast cycle time-low latency dynamic random access memories and systems and methods using the same 138 1996
5,600,606 Low pin count - wide memory devices using non-multiplexed addressing and systems and methods using the same 28 1996
5,906,003 Memory device with an externally selectable-width I/O port and systems and methods using the same 5 1996
5,835,965 Memory system with multiplexed input-output port and memory mapping capability 13 1996
5,829,016 Memory system with multiplexed input-output port and systems and methods using the same 7 1996
5,815,456 Multibank -- multiport memories and systems and methods using the same 24 1996
6,058,464 Circuits, systems and method for address mapping 21 1996
 
SAMSUNG ELECTRONICS CO., LTD. (6)
5,631,871 System for selecting one of a plurality of memory banks for use in an active cycle and all other banks for an inactive precharge cycle 57 1995
5,835,956 Synchronous dram having a plurality of latency modes 48 1997
5,838,990 Circuit in a semiconductor memory for programming operation modes of the memory 46 1997
6,343,036 Multi-bank dynamic random access memory devices having all bank precharge capability 20 1998
6,279,116 Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation 14 1999
6,438,063 Integrated circuit memory devices having selectable column addressing and methods of operating same 21 2000
 
MASSACHUSETTS INSTITUTE OF TECHNOLOGY (3)
8,259,841 Digital transmitter 0 2011
8,238,470 Digital transmitter 0 2011
8,311,147 Digital transmitter 0 2011
 
MICROSEMI CORPORATION (3)
5,592,123 Frequency stability bootstrapped current mirror 5 1995
5,635,852 Controllable actice terminator for a computer bus 21 1995
5,608,312 Source and sink voltage regulator for terminators 35 1995
 
RENESAS ELECTRONICS AMERICA, INC. (3)
5,805,873 Phase linking of output clock with master clock in memory architecture 24 1996
6,065,092 Independent and cooperative multichannel memory architecture for use with master device 139 1997
6,125,421 Independent multichannel memory architecture 41 1998
 
THE UNIVERSITY OF NORTH CAROLINA AT CHAPEL HILL (3)
8,254,491 Digital transmitter 0 2006
8,238,467 Digital transmitter 0 2009
8,243,847 Digital transmitter 0 2009
 
INTEL CORPORATION (2)
6,633,947 Memory expansion channel for propagation of control and request packets 24 1998
6,467,013 Memory transceiver to couple an additional memory channel to an existing memory channel 88 1999
 
LG ELECTRONICS INC. (2)
7,853,662 Network control system for home appliances 0 2001
7,873,699 Network control system for home appliances 3 2004
 
APPLE INC. (1)
5,469,435 Bus deadlock avoidance during master split-transactions 24 1994
 
ELPIDA MEMORY, INC. (1)
7,095,661 Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM 18 2004
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
5,420,987 Method and apparatus for configuring a selected adapter unit on a common bus in the presence of other adapter units 29 1993
 
INTERSIL AMERICAS INC. (1)
7,546,397 Systems and methods for allowing multiple devices to share the same serial lines 0 2007
 
MITSUBISHI DENKI KABUSHIKI KAISHA (1)
6,636,110 Internal clock generating circuit for clock synchronous semiconductor memory device 153 1999
 
NEC CORPORATION (1)
7,902,938 Data transmitter, data transmission line, and data transmission method 0 2005
 
OKI SEMICONDUCTOR CO., LTD. (1)
7,499,321 Semiconductor integrated circuit 0 2007
 
OPTI INC. (1)
7,523,245 Compact ISA-bus interface 1 2006
 
PANASONIC CORPORATION (1)
8,375,238 Memory system 0 2010
 
PERICOM SEMICONDUCTOR CORP. (1)
7,020,208 Differential clock signals encoded with data 6 2002
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (1)
6,952,742 External storage device and method of accessing same 1 2004