Importance

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Abstract

A semiconductor memory unit in which a security code from a security code generation section and an address signal sent from a terminal to the address bus for pseudo access are collated with each other. A control bus changeover circuit connects a control bus to a memory to enable access to the memory when the security code and the address signal coincide with each other. A plurality of memory blocks, each having this security function, are connected in parallel with each other so that the memory blocks have respective independent security functions. A memory block selector selectively provides pseudo access to each of these memory blocks in accordance with an upper address of the address bus. Each memory block is provided with a pseudo access inhibition circuit to inhibit pseudo accessing after the number of pseudo accessing attempts equals a predetermined number.

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First Claim