Control circuit for resetting a snoop valid bit in a dual port cache tag memory
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United States of America Patent
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Jun 7, 1994
Grant Date -
N/A
app pub date -
May 1, 1991
filing date -
May 1, 1991
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A control circuit for a dual port cache tag memory is used to reset a snoop valid bit for an entry addressed through one of the dual ports. This port snoops a main memory bus, and a cache tag hit which occurs during a write operation to the main memory bus indicates that the snoop valid bit for the addressed entry should be reset. In order to avoid errors in resetting the snoop valid bit, which errors can occur due to signal propagation delay, the control circuit resets the snoop valid bit only after a preselected internal delay period.
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