CPU clock generator having a low frequency output during I/O operations and a high frequency output during memory operations
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United States of America Patent
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Jun 7, 1994
Issued Date -
N/A
app pub date -
Apr 26, 1993
filing date -
May 10, 1989
priority date (Note) -
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Abstract
A computer system having a microprocessor that provides bus control signals indicative of bus transaction types such as memory read, memory write, I/O read, and I/O write, generates a variable frequency clock for use by the microprocessor. The computer system also includes a clock generator and a control circuit. The control circuit instructs the clock generator to provide one of a plurality of clock frequencies based on the type of bus transaction specified by the CPU's bus control signals. Typically, I/O transactions cause the control circuit to instruct the clock generator to provide a low frequency clock. In an alternative embodiment, address signals may be used in conjunction with the bus control signals to define which one of a plurality of clock frequencies shall be selected.
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