Method of fabricating a thin-film transistor and wiring matrix device
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United States of America Patent
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Jun 14, 1994
Issued Date -
N/A
app pub date -
Jan 8, 1993
filing date -
Jul 11, 1986
priority date (Note) -
Expired
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Abstract
A method for easily fabricating a thin-film transistor device which has a high reliability. A thin-film transistor is formed on a substrate, the transistor including a first conducting layer deposited on the substrate, a gate insulating layer formed on the first conducting layer, a semiconductor layer deposited on the gate insulating layer, and source and drain electrodes on the semiconductor layer. A multi-layer wiring section is provided adjacent the thin-film transistor, including a first conducting wiring layer formed on the substrate, wiring insulating layer formed on the first conducting wiring layer, and a second conducting wiring layer deposited on the wiring insulating layer and contacting the first conducting wiring layer as well as a portion of the thin-film transistor. The gate insulating layer and the wiring insulating layer are made of the same inorganic material and are of the same thickness.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| FUJI XEROX CO LTD | TOKYO JAPAN TOKYO METROPOLIS |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Kobayashi, Kenichi | Kanagawa, JP | 337 | 4604 |
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| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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