Synchronized, digital sequential circuit
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United States of America Patent
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Jun 14, 1994
Grant Date -
N/A
app pub date -
Mar 1, 1993
filing date -
Feb 27, 1992
priority date (Note) -
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status (Latency Note)
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Abstract
A synchronized, digital sequential circuit includes state-controlled memory elements, each having a clock input, at least two outputs being complementary to one another and at least two inputs, which are connected to a logical OR linkage or wired OR connection. At least two state-controlled memory elements are connected in series. A first memory element performs the OR linkage or operation and a second memory element performs the AND linkage or operation of a combinatorial logic function. The settling time of a memory element and the delay time for forming the OR and AND linkages or operations coincide. Therefore, a high speed of operation is possible in the sequential circuit.
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