Dual-scale topology optoelectronic matrix algebraic processing system
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United States of America Patent
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Jun 14, 1994
Grant Date -
N/A
app pub date -
Mar 2, 1992
filing date -
Mar 2, 1992
priority date (Note) -
Expired
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Abstract
A parallel architecture matrix algebraic processing system exhibits patterns of arrayed (i) light transmitters and (ii) light receivers that are identical, but at differing scales. Planar arrays of one or more optoelectronic processors--principally semiconductor chips or chip arrays--having both computational and light input/output capabilities optically communicate from one plane to the next through free-space space-invariant optical data distributions--principally lenses and computer-generated holograms--having both replication and distribution capabilities. Each optoelectronic processor, or OP, consists of a number of arrayed optoelectronic processing elements, or OPEs. The OPEs, in turn, typically consist of a number of optoelectronic sub-processing units are preferably electrically interconnected in a tree-based structure, preferably an H-tree. Leaf units include typically one light detector plus local memory, logic circuitry, and electrical input/output. Fanning units typically include local memory, logic circuitry, and electrical input/output. A root unit typically includes electrically-connected local memory, logic circuitry, electrical input/output, and a light transmitter. Vector results of algebraic computations and combinations are flexibly performable in the units of each OPE, and variously optically distributable to other OPEs in successive OPs. The versatile algebraic vector manipulations and vector distributions support primitive functions such as intrinsic and extrinsic vector outer products; operations such as vector-matrix multiplication; and complex systems such as neural networks, fuzzy logic and relational databases. A system of .gtoreq.10.sup.3 fully optically communicating OPEs achieves capacities of 10.sup.6 -10.sup.8 interconnects, and processing speeds of 10.sup.12 interconnects/second.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| REGENTS OF THE UNIVERSITY OF CALIFORNIA | BERKELEY CA |
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Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Esener, Sadik C | Solana Beach, CA | 40 | 797 |
| Ford, Joseph E | Solana Beach, CA | 46 | 2052 |
| Krishnamoorthy, Ashok V | San Diego, CA | 216 | 3862 |
| Marsden, Gary C | San Diego, CA | 3 | 47 |
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| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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