Virtual memory management method and apparatus utilizing separate and independent segmentation and paging mechanism
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United States of America Patent
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Jun 14, 1994
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N/A
app pub date -
Apr 9, 1990
filing date -
Jun 13, 1985
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Abstract
Microprocessor architecture for an address translation unit which provides two levels of memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level.
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