Method for manufacturing polyimide multilayer wiring substrate

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5322593
SERIAL NO

07979795

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ATTORNEY / AGENT: (SPONSORED)

Importance

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Abstract

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A layered structure comprising wiring layers and polyimide layers is formed on a ceramics board and a layered structure comprising wiring layers and polyimide layers is formed on an aluminum board. Both the structures are bonded together through adhesives to bring metal bumps formed on the former structure into electric contact with metal bumps formed on the surface of the latter structure and thereafter the aluminum board is removed.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
NEC CORPORATIONTOKYO10436

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hasegawa, Shinichi Tokyo, JP 72 766
Yokokawa, Sakae Tokyo, JP 3 49

Cited Art Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
* 4622058 Formation of a multi-layer glass-metallized structure formed on and interconnected to multi-layered-metallized ceramic substrate 63 1986
* 4970106 Thin film multilayer laminate interconnection board 31 1990
* Cited By Examiner

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
POLARIS INNOVATIONS LIMITED (2)
7221048 Multilayer circuit carrier, panel, electronic device, and method for producing a multilayer circuit carrier 10 2005
* 2005/0151,246 Multilayer circuit carrier, panel, electronic device, and method for producing a multilayer circuit carrier 6 2005
 
SEH AMERICA, INC. (2)
* 5749967 Puller cell 1 1996
* 5702522 Method of operating a growing hall containing puller cells 2 1996
 
NETWORK PROTECTION SCIENCES, LLC (1)
* 5378313 Hybrid circuits and a method of manufacture 63 1993
 
GLOBALFOUNDRIES INC. (4)
6465084 Method and structure for producing Z-axis interconnection assembly of printed wiring board elements 27 2001
6645607 Method and structure for producing Z-axis interconnection assembly of printed wiring board elements 7 2002
7402254 Method and structure for producing Z-axis interconnection assembly of printed wiring board elements 1 2003
* 2004/0052,945 Method and structure for producing Z-axis interconnection assembly of printed wiring board elements 0 2003
 
FormFactor, Inc. (1)
* 6839964 Method for manufacturing a multi-layer printed circuit board 68 2002
 
SAMSUNG ELECTRONICS CO., LTD. (1)
* 2011/0247,871 MULTI-LAYER PRINTED CIRCUIT BOARD COMPRISING FILM AND METHOD FOR FABRICATING THE SAME 2 2011
 
FUJITSU LIMITED (2)
* 5429709 Method of manufacturing polyimide multilayer printed wiring boards 2 1994
* 6389686 Process for fabricating a thin multi-layer circuit board 2 2000
 
SHINKO ELECTRIC INDUSTRIES CO., LTD. (2)
* 6418615 Method of making multilayered substrate for semiconductor device 81 2000
* 6441314 Multilayered substrate for semiconductor device 33 2001
 
HITACHI, LTD. (1)
6423571 Method of making a semiconductor device having a stress relieving mechanism 23 2001
 
UNITED MICROELECTRONICS CORP. (4)
7190823 Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same 7 2002
* 2003/0174,879 Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same 8 2002
7190824 Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same 9 2005
* 2005/0276,465 OVERLAY VERNIER PATTERN FOR MEASURING MULTI-LAYER OVERLAY ALIGNMENT ACCURACY AND METHOD FOR MEASURING THE SAME 2 2005
 
HSBC BANK USA (1)
* 2002/0185,302 Method for manufacturing a multi-layer printed circuit board 0 2002
 
RENESAS ELECTRONICS CORPORATION (1)
* 6028364 Semiconductor device having a stress relieving mechanism 98 1997
 
ZIPTRONIX, INC. (1)
9385024 Room temperature metal direct bonding 0 2014
 
W. L. GORE & ASSOCIATES, INC. (1)
* 6021564 Method for reducing via inductance in an electronic assembly and article 145 1998
 
INVENSAS CORPORATION (2)
* 5557844 Method of preparing a printed circuit board 102 1995
* RE37840 Method of preparing a printed circuit board 2 1998
 
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (1)
* 6586825 Dual chip in package with a wire bonded die mounted to a substrate 7 2001
* Cited By Examiner