US Patent No: 5,322,593

Number of patents in Portfolio can not be more than 2000

Method for manufacturing polyimide multilayer wiring substrate

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Abstract

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A layered structure comprising wiring layers and polyimide layers is formed on a ceramics board and a layered structure comprising wiring layers and polyimide layers is formed on an aluminum board. Both the structures are bonded together through adhesives to bring metal bumps formed on the former structure into electric contact with metal bumps formed on the surface of the latter structure and thereafter the aluminum board is removed.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
NEC CORPORATIONTOKYO18334

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hasegawa, Shinichi Joetsu, JP 82 657
Yokokawa, Sakae Tokyo, JP 3 35

Cited Art Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
4,622,058 Formation of a multi-layer glass-metallized structure formed on and interconnected to multi-layered-metallized ceramic substrate 52 1986
4,970,106 Thin film multilayer laminate interconnection board 31 1990

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (3)
6,465,084 Method and structure for producing Z-axis interconnection assembly of printed wiring board elements 24 2001
6,645,607 Method and structure for producing Z-axis interconnection assembly of printed wiring board elements 7 2002
7,402,254 Method and structure for producing Z-axis interconnection assembly of printed wiring board elements 0 2003
 
FUJITSU LIMITED (2)
5,429,709 Method of manufacturing polyimide multilayer printed wiring boards 1 1994
6,389,686 Process for fabricating a thin multi-layer circuit board 2 2000
 
INVENSAS CORPORATION (2)
5,557,844 Method of preparing a printed circuit board 96 1995
RE37840 Method of preparing a printed circuit board 2 1998
 
SEH AMERICA, INC. (2)
5,749,967 Puller cell 1 1996
5,702,522 Method of operating a growing hall containing puller cells 2 1996
 
SHINKO ELECTRIC INDUSTRIES CO., LTD. (2)
6,418,615 Method of making multilayered substrate for semiconductor device 61 2000
6,441,314 Multilayered substrate for semiconductor device 33 2001
 
UNITED MICROELECTRONICS CORP. (2)
7,190,823 Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same 4 2002
7,190,824 Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same 8 2005
 
FormFactor, Inc. (1)
6,839,964 Method for manufacturing a multi-layer printed circuit board 65 2002
 
HITACHI, LTD. (1)
6,423,571 Method of making a semiconductor device having a stress relieving mechanism 8 2001
 
LSI LOGIC CORPORATION (1)
6,586,825 Dual chip in package with a wire bonded die mounted to a substrate 7 2001
 
NETWORK PROTECTION SCIENCES, LLC (1)
5,378,313 Hybrid circuits and a method of manufacture 55 1993
 
QIMONDA AG (1)
7,221,048 Multilayer circuit carrier, panel, electronic device, and method for producing a multilayer circuit carrier 6 2005
 
RENESAS ELECTRONICS CORPORATION (1)
6,028,364 Semiconductor device having a stress relieving mechanism 66 1997
 
W. L. GORE & ASSOCIATES, INC. (1)
6,021,564 Method for reducing via inductance in an electronic assembly and article 118 1998