Computer system including a write protection circuit for preventing illegal write operations and a write poster with improved memory
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United States of America Patent
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-
Jun 28, 1994
Grant Date -
N/A
app pub date -
Sep 28, 1990
filing date -
Sep 28, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A computer system including a write protection circuit and a write poster is disclosed. The write protection circuit provides page description information to the computer system for controlling various operations. Illegal write operations as defined by the page description information are prevented from reaching a system bus and external cache. Internal cache invalidate operations may also be performed transparently to system operation. The write poster accepts write operations in zero wait states and assembles them into fewer more efficient writes to memory. A unique method and apparatus for programming a descriptor random access memory (RAM) is also provided.
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