Importance

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Abstract

An associative memory is provided having a first control bus arrangement (any type, Vr, cpb, set.s, match, r/w.s, r/w.b, r/w.r, Wand.a, Wand.b, Wor, s.a, reset.b, mode.a mode.a*, prech, ba, mode.b, grant.b, prio etc) for external control and a second memory bus arrangement (t1, t2, id, anv, v0, v1, v2, v3) for data. The memory includes several storage cells (1) for storing a composed information. Each storage cell stores at least one mark, which indicates at least select state(s) or non select state(s) for said storage cell. The mark(s) are set by search operations among said cells. A priority decoder (2) is provided to which all said storage cells are coupled and which selects one out of several of said storage cells. At least one global bus (4, 5) is provided for making logical operations of the type AND and OR between said storage cells. A closure head (11) is provided in each storage cell for communicating with said buses and to control said storage cell to take part in an actual logical operation. Each storage cell includes a number of data object storage fields (IDENTITY, ENVIRONMENT, VALUE/DES..sub.0, VALUE/DES..sub.1, VALUE/DES..sub.2, VALUE/DES..sub.3), which are able to store a data word and at least one of said marks, being in form of tags.

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First Claim