Importance

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Abstract

A symmetric pipelined charge-mode analog to digital converter including a signal-reference CCD channel having a plurality of charge storage stages that are arranged in a serial configuration to carry the signal and reference charges, and a CCD digital channel. A set of two step comparators coupled to the signal-reference channel first senses and stores the signal charge and then senses and compares the reference charge to the signal charge. In the first stage, an initial reference charge is used, and in subsequent stages, an increment of one half the previous stage increment is added to the reference. In addition, at each stage, a charge increment equal to the previous reference increment is conditionally added to the signal charge and a corresponding bit in the digital channel is conditionally set responsive to the comparator. Thus, if the total signal charge is less than the total reference charge at a stage, the charge increment is added to the signal charge in the signal-reference channel, and a corresponding digital bit charge is zeroed in the digital channel. Conversely, if the total signal charge is larger than the told reference charge at a stage, the charge increment is not added to the signal charge and a corresponding digital bit charge is set to represent a one in the digital channel. One configuration provides a differential symmetric architecture wherein two signal-reference channels simultaneously feed a dual symmetric comparator providing enhanced symmetry thereby reducing threshold and offset sensitivity and susceptibility to environmental factors such as ionizing radiation.

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First Claim