Three dimensional assembly of integrated circuit chips
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United States of America Patent
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Jul 5, 1994
Grant Date -
N/A
app pub date -
Oct 30, 1992
filing date -
Oct 30, 1992
priority date (Note) -
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status (Latency Note)
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Abstract
The multi-chip circuit module of the invention comprises a plurality of circuit chips assembled in a laminated stack. Each chip includes a plurality of layers of thin film interconnect patterns in the normal configuration, except for the final layer or layers, which comprise a reroute pattern that locates all circuit input and output pads along a single edge of each chip. The relocated pads are provided with contact bumps to facilitate the addition of a bonded lead to each I/O pad extending therefrom to a point beyond the edge of each chip. Thus, upon lamination the protruding tips form an array of leads on a single lateral face of the laminated chip stack.
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