Redundancy selection apparatus and method for an array
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United States of America Patent
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Jul 5, 1994
Grant Date -
N/A
app pub date -
Jun 3, 1992
filing date -
Jun 3, 1992
priority date (Note) -
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status (Latency Note)
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Abstract
A fused decoder for selecting one or more elements of an array, such as a row of memory, is provided. The corresponding row of memory can be permanently deselected by blowing the fuse of the decoder. Array components such as a redundant row of memory, can be substituted for the deselected component. The decoder includes a gate formed exclusively from NMOS transistors so that the decoder can provide a select signal in response to an address without an PMOS transistor responding to the address- By eliminating PMOS transistors from the gate portion of the decoder, the load presented to the address lines is reduced.
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