Lead-on-chip inner lead bonding lead frame method and apparatus
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United States of America Patent
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Jul 19, 1994
Grant Date -
N/A
app pub date -
Sep 30, 1992
filing date -
Sep 30, 1992
priority date (Note) -
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Abstract
A multi-level lead frame configuration (114) for an integrated circuit chip (116) comprises a main lead frame (115) having a plurality of lead frame bond fingers (122 and 124) that directly connect to a plurality of bond pads (126) on the integrated circuit chip (116). Associated with the main lead frame (115) is a bus bar lead frame (128 and 130) having a plurality of bus bar lead fingers (118 and 120) that directly connect to a second plurality of inner bond pads (126) on the integrated circuit chip (116). The bus bar bond fingers (118 and 120) associate with the main lead frame (115) and main lead frame bond fingers (122 and 124) to permit a lead-on-chip configuration of the main lead frame and the bus bar lead frame.
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