Multi-chip semiconductor package

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United States of America Patent

PATENT NO 5332922
SERIAL NO

07691985

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Abstract

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A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

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Patent Owner(s)

Patent OwnerAddress
ELPIDA MEMORY INCTOKYO TOKYO METROPOLIS

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Anjoh, Ichiro Koganei, JP 78 1689
Ishihara, Masamichi Hamura, JP 72 1690
Ito, Kazuya Hamura, JP 38 627
Kasama, Yasuhiro Tokyo, JP 24 509
Matsuno, Youichi Koganei, JP 3 178
Miyamoto, Eiji Ohme, JP 41 699
Murakami, Gen Tama, JP 83 2828
Nozoe, Atsusi Ohme, JP 3 178
Oguchi, Satoshi Ohme, JP 36 464
Sakuta, Toshiyuki Ohme, JP 27 776
Satoh, Hiroshi Kodaira, JP 162 2384
Udagawa, Tetsu Iruma, JP 15 456
Yamaguchi, Yasunori Ohme, JP 43 836

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